Formal verification

Others have gone here before me, and now it is my turn! Formal verification is a tool for verifying the correctness of your implementation. Traditional verification strategies have relied on hand-crafted testbenches to provide stimuli to the DUT. Formal verification aims to automate that process.

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greenblat/vlsistuff

vlsistuff ideas and eda software for vlsi design genver: macro preprossor on verilog files, to aid in writing long verilog structures. synlib: turning liberty format files into what You need: simulation and more. vcd_python: reading vcd files and making sense out of them.

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