Our ECE 5760 Final Project uses the Terasic DE1-SoC’s Cyclone V FPGA and Cortex-A9 cores to fully simulate a Xilinx XC6200 FPGA. We test the functionity of the hardware-simulated FPGA and experiment on its ability to discern between input frequences using a genetic algorithm.
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Welcome to FuseSoC’s documentation!¶
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Heterogeneous SoCs like the Zynq and Zynq MPSoC are ideal for image processing as they allow the implementation of the image processing pipeline in the PL. While the PS can implement the higher levels of the algorithm and decision making.
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