Symbolator is a component diagramming tool for VHDL and Verilog. It will parse HDL source files, extract components or modules and render them as an image. Symbolator can render to PNG bitmap images or SVG, PDF, PS, and EPS vector images. SVG is the default.
A Field-Programmable Gate Array (FPGA) can implement arbitrary digital logic, anything from a microprocessor to a video generator or crypto miner.