Others have gone here before me, and now it is my turn! Formal verification is a tool for verifying the correctness of your implementation. Traditional verification strategies have relied on hand-crafted testbenches to provide stimuli to the DUT. Formal verification aims to automate that process.
Recently a squirrel noticed our nut box that was waiting to be raided for almost a year now. But as our squirrels here are a but skittish, I needed to come up with a way to get in close to take nice pictures of them.
vlsistuff ideas and eda software for vlsi design genver: macro preprossor on verilog files, to aid in writing long verilog structures. synlib: turning liberty format files into what You need: simulation and more. vcd_python: reading vcd files and making sense out of them.
As cheesy as the title sounds, I promise it cannot beat the cheesiness of the technique I’ll be telling you about in this post.
Bluetooth Low Energy (BLE) is everywhere these days. If you fire up a scanner on your phone and walk around the neighborhood, we’d be willing to bet you’d pick up dozens if not hundreds of devices.
Xilinx has committed their infrastructure to AXI. Zynq’s are built around AXI3, while most of the Vivado generated infrastructure within their FPGA environment is now AXI4.
If you enjoy simulating circuits, you’ve probably used LTSpice. The program has a lot of powerful features we tend to not use, including the ability to make custom components that are quite complex.
For American readers of a certain age, Local on the 8s likely holds a special spot in your heart.