This blog posts was also published on the YosysHQ blog. If you’re reading this you probably already know that Yosys is an open source logic synthesis tool.
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For my open source RTL projects, I’ve so far only used 2 Verilog simulators: Icarus Verilog and Verilator.
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Formal Verification uses mathematical techniques to exhaustively prove that a property, or an obligation that must hold in a system, is proven under all possible conditions or inputs of an RTL design.
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Ayant préparé tout le matériel pour faire du TapTempo en Verilog, il était trop tentant de réaliser la même chose en VHDL. L’occasion de se plonger dans ce langage de description matériel concurrent du Verilog.
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