This guest post is by Theophile Loubiere. Recently, I began using SBY to formally verify my designs. You can check out my first attempt on my blog learn-fpga-easily. Formal Verification helps ensure that certain properties of your design always remain true, such as:
from Pocket
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Others have gone here before me, and now it is my turn! Formal verification is a tool for verifying the correctness of your implementation. Traditional verification strategies have relied on hand-crafted testbenches to provide stimuli to the DUT. Formal verification aims to automate that process.
from Pocket
via Did you enjoy this article? Then read the full version from the author’s website.