Tag Archives: reblog

Getting Started with OPENOCD Using FT2232H Adapter for SWD Debugging

Old MCUs from vendors like ATMEL and MICROCHIP, like the PIC16F and Atmega family, tend to have a special programming interface to program internal flash. For example, Atmega used SPI pins (MISO, MOSI, SCK) and PIC used two pins (PGC, PGD)— one as a clock and another as a bi-directional data line.

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Symbi­Flow – open source FPGA tooling for rapid innov­ation

Symbi­Flow – open source FPGA tooling for rapid innov­ation SymbiFlow is a work-in-progress FOSS Verilog-to-Bitstream (end-to-end) FPGA synthesis flow, currently targeting Xilinx 7-Series, Lattice iCE40 and Lattice ECP5 FPGAs. Think of it as the GCC of FPGAs.

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1. Table of Contents¶

In this tutorial, VHDL is used to implement various designs on FPGA board. All the designs are tested on the FPGA boards. NIOS II processor is also used for designs. In this tutorial, Verilog is used to implement various designs on FPGA board. All the designs are tested on the FPGA boards.

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Hitchhiker’s Guide to the WaveDrom

WaveDrom is a JavaScript application. WaveJSON is a format that describes Digital Timing Diagrams. WaveDrom renders the diagrams directly inside the browser. Element “signal” is an array of WaveLanes. Each WaveLane has two mandatory fields: “name” and “wave”. Step 1.

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La libération des FPGA et des ASIC bien engagée pour 2020

En début d’année 2019 se posait la question de savoir si ce serait l’année de la libération des FPGA. En ce début d’année 2020, essayons de faire un bilan. FPGA, ASC, HDL, RISC‑Ⅴ et PCB sont les chapitres que nous allons découvrir dans la suite de cet article.

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